摘要
A systematic investigation is presented about the robustness of logic synthesis tools to equivalence-preserving transformations of the input Verilog file. We have developed a framework that: 1) parses Verilog behavioral models into an abstract syntax tree; 2) generates random equivalence-preserving transformations on the syntax tree, and; 3) writes the transformed design back in Verilog format. The original and the transformed Verilog descriptions are then checked for equivalence and synthesized. Results show that average (peak) improvements in area of 2.5% (11%) and length of the critical path of 4% (13%) are achievable. Indeed these figures are comparable to recent advancements in logic synthesis ([17] [8] achieve 4.9% (23%) 5% (24%) improvements area-wise, respectively), signaling a relevant lack of robustness in synthesis tools. This lack of robustness suggests that new synthesis algorithms should be evaluated by measuring the average improvement on several transformed files to assess their real contributions to the quality of the results.
摘要译文
介绍了关于逻辑综合工具对输入Verilog文件的等效保存变换的鲁棒性的系统调查我们开发了一个框架：1）将Verilog行为模型解析为抽象语法树; 2）在语法树上生成随机等效保存变换，3）将转换的设计写回Verilog格式。然后检查原始和转换后的Verilog描述等价和合成的结果表明，可以实现2 5（11％25）和4％25（13％25）关键路径的平均（峰值）改善实际上，这些数字与最近在逻辑综合方面取得的进步（[17] [8]）分别实现了4 5（23％25）5％25（24％25）分别改善）表明综合工具相关缺乏鲁棒性鲁棒性表明，应该通过测量几个转换文件的平均改进来评估新的综合算法，以评估其对结果的质量的真正贡献
Alberto Puggelli[1];Tobias Welp[1];Andreas Kuehlmann[1];Alberto Sangiovanni-Vincentelli[1]. Are logic synthesis tools robust?[C]//DAC '11:Proceedings of the 48th Design Automation Conference, San Diego, CA, USA , June 05 - 10, 2011, CA: ACM, 2011: 633-638