摘要
A systematic investigation is presented about the robustness of logic synthesis tools to equivalence-preserving transformations of the input Verilog file. We have developed a framework that: 1) parses Verilog behavioral models into an abstract syntax tree; 2) generates random equivalence-preserving transformations on the syntax tree, and; 3) writes the transformed design back in Verilog format. The original and the transformed Verilog descriptions are then checked for equivalence and synthesized. Results show that average (peak) improvements in area of 2:5%(11%) and length of the critical path of 4%(13%) are achievable. Indeed these figures are comparable to recent advancements in logic synthesis (achieve 4:9%(23%) 5%(24%) improvements area-wise, respectively), signaling a relevant lack of robustness in synthesis tools. This lack of robustness suggests that new synthesis algorithms should be evaluated by measuring the average improvement on several transformed files to assess their real contributions to the quality of the results.
摘要译文
一个系统的调查，提出了关于逻辑综合工具的稳健性，以等价保输入的Verilog文件的转换。我们已经制定了一个框架：1）分析Verilog的行为模型为一个抽象语法树; 2）产生的语法树无规等价保变换，和;3）写的转化设计早在Verilog的格式。原始和转化的Verilog描述，然后检查等价和合成。结果表明，在2面积平均值（峰值）的改善：5％（11％）和4％（13％）的关键路径的长度是可以实现的。事实上，这些数字媲美最新发展逻辑综合（实现4：分别为9％（23％），5％（24％），改善区域方式，），信号相关的缺乏稳健性的综合工具。鲁棒性表明，新合成的算法应通过测量在几个变换文件的平均改善，以评估其对结果的质量真正的贡献进行评估。
Puggelli, A.; Welp, T.; Kuehlmann, A.; Sangiovanni-Vincentelli, A.;. Are logic synthesis tools robust?[C]//Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, San Diego, CA, USA, 5-9 June 2011, CA: IEEE, 2011: -