摘要
The chapter discussed a few basic questions on the usage of Verilog constructs during assignments and usage in task, function, port, and parameter. The chapter discusses the different approach of parameter and port specifications. A few SystemVerilog enhancements to the task and function have also been discussed. The next chapter discusses how the Verilog constructs are useful under the synthesis context.
摘要译文
本章讨论的Verilog上的使用几个基本的问题在分配和使用情况的任务，功能，端口和参数构造。本章讨论的参数和接口的规格不同的方法。几SystemVerilog的增强任务和功能也进行了讨论。下一章讨论Verilog的结构是如何合成环境下是有用的。
Basic Verilog. Verilog: Frequently Asked Questions[M].DE: springer, 2004: 1-34