摘要
Disclosed is a cache memory for transferring data efficiently between the processors in a multi-processor system having a shared cache memory. The disclosed cache memory has a tag storage section (220) storing a plurality of entries, each entry storing a tag address (221), a valid flag (222), a dirty flag (223), and the number of times referenced (224). The number of times referenced (224) is set when the data is written in and is decremented upon each read access. When the number of times referenced (224) is decremented from "1" to "0", the entry in question is invalidated without being written back. The disclosed cache memory functions as a shared FIFO memory when used for communication between the processors in a multi-processor system, and data that have been used are deleted automatically.
摘要译文
Disclosed is a cache memory for transferring data efficiently between the processors in a multi-processor system having a shared cache memory. The disclosed cache memory has a tag storage section (220) storing a plurality of entries, each entry storing a tag address (221), a valid flag (222), a dirty flag (223), and the number of times referenced (224). The number of times referenced (224) is set when the data is written in and is decremented upon each read access. When the number of times referenced (224) is decremented from "1" to "0", the entry in question is invalidated without being written back. The disclosed cache memory functions as a shared FIFO memory when used for communication between the processors in a multi-processor system, and data that have been used are deleted automatically.
HIRAO Taichi (1-7-1 Konan, Minato-k, Tokyo 75, 〒1080075, JP) 平尾 太一 (〒75 東京都港区港南１丁目７番１号 ソニー株式会社内 Tokyo, 〒1080075, JP) SAKAGUCHI Hiroaki (1-7-1 Konan, Minato-k, Tokyo 75, 〒1080075, JP) 坂口 浩章 (〒75 東京都港区港南１丁目７番１号 ソニー株式会社内 Tokyo, 〒1080075, JP). CACHE MEMORY AND CACHE MEMORY CONTROL DEVICE: WIPO Patent Application WO/2011/078014[P]. 06/30/2011: