摘要
A cache memory (6) includes: a data storage unit (16) having a line containing four words (Word0, Word1, Word2, Word3); and a tag storage unit (14) which stores a tag for identifying each line. The tag storage unit contains a refill bit (R), dirty bits (D0, D1, D2, D3), and a tag bit (Tag). If a tag address (AD [31:16]) to be accessed coincides with the address indicated in the tag bit (Tag) and if the refill bit (R) corresponding to the line relating to the access object indicates that refill is in progress, a hit check unit (20) determines that the write access is a write hit. If the dirty bit corresponding to the word relating to the access object contained in the line indicates dirty, the hit check unit (20) determines that the read access is a read hit.
摘要译文
A cache memory (6) includes: a data storage unit (16) having a line containing four words (Word0, Word1, Word2, Word3); and a tag storage unit (14) which stores a tag for identifying each line. The tag storage unit contains a refill bit (R), dirty bits (D0, D1, D2, D3), and a tag bit (Tag). If a tag address (AD [31:16]) to be accessed coincides with the address indicated in the tag bit (Tag) and if the refill bit (R) corresponding to the line relating to the access object indicates that refill is in progress, a hit check unit (20) determines that the write access is a write hit. If the dirty bit corresponding to the word relating to the access object contained in the line indicates dirty, the hit check unit (20) determines that the read access is a read hit.
HASHIMOTO, Yoshinobu (()). CACHE MEMORY AND CACHE MEMORY SYSTEM: WIPO Patent Application WO/2010/029694[P]. 03/18/2010: