摘要
It is possible to prevent increase of latency in a subsequent memory access by using all the MSHR (Miss Status/Information Holding Register) in a non-blocking cache. Provided is a cache memory including: a plurality of MSHR; a memory access identification means which identifies a memory access contained in a received memory access request; and a memory access correlation means which correlates a memory access with an MSHR used when the memory access causes a cache miss and determines an MSHR candidate to be used by the memory access identified in the access identification means according to the correlation.
摘要译文
It is possible to prevent increase of latency in a subsequent memory access by using all the MSHR (Miss Status/Information Holding Register) in a non-blocking cache. Provided is a cache memory including: a plurality of MSHR; a memory access identification means which identifies a memory access contained in a received memory access request; and a memory access correlation means which correlates a memory access with an MSHR used when the memory access causes a cache miss and determines an MSHR candidate to be used by the memory access identified in the access identification means according to the correlation.
ISHIZAKA, Kazuhisa (7-1 Shiba 5-chome, Minato-k, Tokyo 14, 〒1080014, JP) 石坂 一久 (〒14 東京都港区芝五丁目７番１号 日本電気株式会社内 Tokyo, 〒1080014, JP). CACHE MEMORY, CACHE MEMORY SYSTEM, AND METHOD AND PROGRAM FOR USING THE CACHE MEMORY: WIPO Patent Application WO/2010/024071[P]. 03/04/2010: