摘要
A cache memory comprises ways (0 to 3) and a control unit. For each cache entry, the ways (0 to 3) store a usage flag U to indicate whether an access is made or not. When a hit occurs, the control unit updates the usage flag U corresponding to the cache entry to the one indicating that an access is made. At this time, if all the other usage flags in the set each indicate that an access is made, the control unit resets all the other usage flags in the set to the ones each indicating that no access is made and, from the cache entries corresponding to the usage flags each indicating that no access is made, selects a cache entry to be replaced.
摘要译文
A cache memory comprises ways (0 to 3) and a control unit. For each cache entry, the ways (0 to 3) store a usage flag U to indicate whether an access is made or not. When a hit occurs, the control unit updates the usage flag U corresponding to the cache entry to the one indicating that an access is made. At this time, if all the other usage flags in the set each indicate that an access is made, the control unit resets all the other usage flags in the set to the ones each indicating that no access is made and, from the cache entries corresponding to the usage flags each indicating that no access is made, selects a cache entry to be replaced.
Tanaka, Tetsuya Nakanishi, Ryuta Kiyohara, Tokuzou Morishita, Hiroyuki Chikamura, Keishi. CACHE MEMORY AND CACHE MEMORY CONTROL METHOD: WIPO Patent Application WO/2005/029336[P]. 03/31/2005: