摘要
Verilog is a very popular Hardware Description language (HDL) that is used to model the digital systems. The Verilog HDL can be used at different abstraction levels like from gate level to system design level. This means that a digital circuit can be described by the hardware connectivity or by writing only the behaviour of the circuit. It may be the timing model or the behaviour of the circuit, Verilog provides an easy platform to realize the digital circuits. Thus Verilog HDL provides an easy platform for rapid modelling of the digital circuits.
摘要译文
Verilog is a very popular Hardware Description language (HDL) that is used to model the digital systems. The Verilog HDL can be used at different abstraction levels like from gate level to system design level. This means that a digital circuit can be described by the hardware connectivity or by writing only the behaviour of the circuit. It may be the timing model or the behaviour of the circuit, Verilog provides an easy platform to realize the digital circuits. Thus Verilog HDL provides an easy platform for rapid modelling of the digital circuits.
Shirshendu Roy[1]. Basics of Verilog HDL. Advanced Digital System Design[M].DE: Springer, 2024: 15-38