图书章节

Basics of System Verilog 收藏

Basics of System Verilog
原文求助 发布源
作者
Shirshendu Roy[1]
作者单位
[1]Department of Electronics and Communication Engineering, Dayananda Sagar University, Bengaluru, India
发布日期
26 September 2023
页码
391-423
DOI
10.1007/978-3-031-41085-7_17
来源信息
Advanced Digital System Design ISBN：9783031410871, 2024年, 391-423页
摘要
In the Chap. 3, we have discussed the fundamentals of Verilog HDL which is the most used language for description of hardware. In the case of FPGA implementations Verilog was enough as timing verification is mostly handled by the EDA tools. But for ASIC designs designers were using other tools to perform STA and other verification tasks.
摘要译文
In the Chap. 3, we have discussed the fundamentals of Verilog HDL which is the most used language for description of hardware. In the case of FPGA implementations Verilog was enough as timing verification is mostly handled by the EDA tools. But for ASIC designs designers were using other tools to perform STA and other verification tasks.
Shirshendu Roy[1]. Basics of System Verilog. Advanced Digital System Design[M].DE: Springer, 2024: 391-423