摘要
During the design of any circuit, delays must be considered in the programming to match with actual hardware timings. Three different types of delay modeling are available in Verilog, namely distributed-delay modeling, lumped-delay modeling, and pin-to-pin-delay modeling or path-delay modeling. Verilog has a number of built-in primitives that can be illustrated in modules viz. gate type. Verilog enables the user to create their own primitives called user-defined primitives (UDP). In UDP, the user describes any logic with the help of a truth table. In Verilog, task and function are available to fulfill the requirements of subroutines. Some similarities between task and function are both function and task are defined in a module and belong to that particular module. Wires are not used in any task or function. They are constructed only from behavioral statements.
摘要译文
在任何电路的设计期间，必须在编程中考虑延迟，以与实际的硬件计时匹配。Verilog中有三种不同类型的延迟建模，即分布式 - 延迟建模，集总模型以及销钉到针 - 戴式建模或路径 - 延迟建模。Verilog有许多内置的原始图，可以在模块中说明。门类型。Verilog使用户能够创建自己的原始词，称为用户定义的原语（UDP）。在UDP中，用户在真实表的帮助下描述了任何逻辑。在Verilog中，任务和功能可用于满足子例程的要求。任务和功能之间的一些相似之处既是功能，又在模块中定义了任务，并且属于该特定模块。电线不在任何任务或功能中使用。它们仅由行为陈述构建。
Advance Verilog Topics. Digital VLSI Design and Simulation with Verilog[M].US: Wiley, 2021: 135-149