博硕论文

CAD tools for synthesis of sleep convention logic 收藏

合成睡眠习惯的逻辑CAD工具

原文求助

学校

University of Arkansas(阿肯色大学)

作者

Palangpour, Parviz M.

关键词

Applied sciences, Sleep convention logic, ASIC, Asynchronous logic, Low-power

关键词译文

应用科学，睡眠习惯逻辑， ASIC ，异步逻辑，低功耗

发布日期

AI-B 74/08(E), Feb 2014

来源信息

University of Arkansas，学位：Ph.D.，导师：Smith, Scott C., 2013年, 85页

摘要

This dissertation proposes an automated flow for the Sleep Convention Logic (SCL) asynchronous design style. The proposed flow synthesizes synchronous RTL into an SCL netlist. The flow utilizes commercial design tools, while supplementing missing functionality using custom tools. A method for determining the performance bottleneck in an SCL design is proposed. A constraint-driven method to increase the performance of linear SCL pipelines is proposed. Several enhancements to SCL are proposed, including techniques to reduce the number of registers and total sleep capacitance in an SCL design.

摘要译文

本文提出的睡眠公约逻辑（ SCL ）的异步设计风格的自动化流程。建议的流程同步合成RTL到网表SCL 。该流程利用商业设计工具，同时补充缺失的功能使用自定义的工具。一种用于确定在发生SCL设计的性能瓶颈方法。约束驱动的方法来增加线性SCL管道的性能提出。几项改进SCL提出，包括技术，以减少在SCL设计寄存器和总睡眠电容的数量。

Palangpour, Parviz M.. CAD tools for synthesis of sleep convention logic[D]. US: University of Arkansas, 2013