摘要
Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from "1" to "0", the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.
摘要译文
Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from "1" to "0", the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.
Hirao, Taichi c/o SONY CORPORATION1-7-1 (KonanMinato-ku, Tokyo 108-0075, JP) Sakaguchi, Hiroaki c/o SONY CORPORATION1-7-1 (KonanMinato-ku, Tokyo 108-0075, JP) Yoshikawa, Hiroshi c/o SONY CORPORATION1-7-1 (KonanMinato-ku, Tokyo 108-0075, JP) Ishii, Masaaki c/o SONY CORPORATION1-7-1 (KonanMinato-ku, Tokyo 108-0075, JP). CACHE MEMORY AND CACHE MEMORY CONTROL DEVICE: European Patent Application EP2518633[P]. 10/31/2012: