摘要
High density programmable logic devices require dedicated synthesis algorithms to maximize the utilization of the device resources. The authors discuss the impact of device architectures on logic synthesis algorithms, and show how device specific optimization allows designers to design for multiple architectures from a common design description. The Exemplar Logic synthesis system combines industry standard design entry methods with architecture specific optimization algorithms. This power lets designers easily migrate PLD, FPGA, or ASIC designs to FPGAs or ASICs, and gives designers using top-down design techniques the flexibility to explore speed versus area tradeoffs between FPGAs and ASICs early in the design cycle.
摘要译文
高密度可编程逻辑器件需要专门的综合算法来最大限度地利用器件资源。作者讨论了器件架构对逻辑综合算法的影响，并展示了器件特定优化如何允许设计人员从通用设计描述Exemplar Logic综合系统将行业标准设计输入方法与特定于体系结构的优化算法结合在一起。这种功能使设计人员能够轻松地将PLD，FPGA或ASIC设计迁移到FPGA或ASIC，并使设计师能够使用自上而下的设计技术，在设计周期早期FPGA和ASIC之间的面积权衡
M. Ligthart[1];R. Ranauro[1]. The Exemplar Logic synthesis system: a logic synthesis tool for field programmable gate arrays[C]//ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International, Rochester, NY (127);Rochester, NY, USA (1), 23-27 Sept. 1991, CA: IEEE, 1991: 2/1-P13